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publications

PipeFuser: Building Flexible Pipeline Architecture for DNN Accelerators via Layer Fusion

Published in 29th ASP-DAC 2024, Incheon, South Korea, 2024

PipeFuser introduces a layer fusion-based design framework that constructs flexible and high-throughput DNN pipelines on FPGAs, improving both resource utilization and latency.

Recommended citation: X. Zhou, S. Li, H. Lu, K. Wang. "PipeFuser: Building Flexible Pipeline Architecture for DNN Accelerators via Layer Fusion." ASP-DAC, 2024.
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DNNMapper: an Elastic Framework for Mapping DNNs to Multi-Die FPGAs

Published in IEEE ISCAS 2024, Singapore, 2024

DNNMapper is an elastic mapping framework that supports scalable deployment of deep neural networks onto multi-die FPGA platforms. The framework supports efficient partitioning and inter-die communication.

Recommended citation: S. Li, X. Zhou, H. Lu, K. Wang. "DNNMapper: an Elastic Framework for Mapping DNNs to Multi-Die FPGAs." ISCAS, 2024.
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FPGA-Based Sparse Matrix Multiplication Accelerators: From State-of-the-art to Future Opportunities

Published in ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2024

This survey reviews the state-of-the-art in sparse matrix multiplication on FPGAs, identifying architectural trends, bottlenecks, and opportunities for future research and design automation.

Recommended citation: Y. Liu, R. Chen, S. Li, J. Yang, S. Li, B. da Silva. "FPGA-Based Sparse Matrix Multiplication Accelerators: From State-of-the-art to Future Opportunities." ACM TRETS, 2024. DOI: 10.1145/3687480
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DIF-LUT Pro: An Automated Tool for Simple yet Scalable Approximation of Nonlinear Activation on FPGA

Published in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2025

DIF-LUT Pro enables simple and scalable approximation of nonlinear activation functions on FPGAs. This paper presents its automation flow and accuracy-resource tradeoffs validated on multiple benchmarks.

Recommended citation: Y. Liu, S. Li, R. Chen, Y. Li, J. Yu, K. Wang. "DIF-LUT Pro: An Automated Tool for Simple yet Scalable Approximation of Nonlinear Activation on FPGA." IEEE TCAD, 2025. DOI: 10.1109/TCAD.2025.3576333
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TrackGNN: A Highly Parallelized and FIFO-Balanced GNN Accelerator for Track Reconstruction on FPGAs

Published in 33rd IEEE FCCM 2025, 2025

This paper proposes TrackGNN, a highly parallelized GNN accelerator designed for efficient track reconstruction in high energy physics. We introduce a FIFO-balanced architecture optimized for FPGA implementation, achieving state-of-the-art performance.

Recommended citation: S. Li, H. Zhang, R. Chen, C. Hao. "TrackGNN: A Highly Parallelized and FIFO-Balanced GNN Accelerator for Track Reconstruction on FPGAs." 33rd IEEE FCCM, 2025.
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teaching

Teaching experience 1

Undergraduate course, University 1, Department, 2014

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Teaching experience 2

Workshop, University 1, Department, 2015