Sitemap

A list of all the posts and pages found on the site. For you robots out there, there is an XML version available for digesting as well.

Pages

Posts

Future Blog Post

less than 1 minute read

Published:

This post will show up by default. To disable scheduling of future posts, edit config.yml and set future: false.

Blog Post number 4

less than 1 minute read

Published:

This is a sample blog post. Lorem ipsum I can’t remember the rest of lorem ipsum and don’t have an internet connection right now. Testing testing testing this blog post. Blog posts are cool.

Blog Post number 3

less than 1 minute read

Published:

This is a sample blog post. Lorem ipsum I can’t remember the rest of lorem ipsum and don’t have an internet connection right now. Testing testing testing this blog post. Blog posts are cool.

Blog Post number 2

less than 1 minute read

Published:

This is a sample blog post. Lorem ipsum I can’t remember the rest of lorem ipsum and don’t have an internet connection right now. Testing testing testing this blog post. Blog posts are cool.

Blog Post number 1

less than 1 minute read

Published:

This is a sample blog post. Lorem ipsum I can’t remember the rest of lorem ipsum and don’t have an internet connection right now. Testing testing testing this blog post. Blog posts are cool.

portfolio

publications

DNNMapper: an Elastic Framework for Mapping DNNs to Multi-Die FPGAs

Published in IEEE ISCAS 2024, Singapore, 2024

DNNMapper is an elastic mapping framework that supports scalable deployment of deep neural networks onto multi-die FPGA platforms. The framework supports efficient partitioning and inter-die communication.

Recommended citation: S. Li, X. Zhou, H. Lu, K. Wang. "DNNMapper: an Elastic Framework for Mapping DNNs to Multi-Die FPGAs." ISCAS, 2024.
Download Paper

FPGA-Based Sparse Matrix Multiplication Accelerators: From State-of-the-art to Future Opportunities

Published in ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2024

This survey reviews the state-of-the-art in sparse matrix multiplication on FPGAs, identifying architectural trends, bottlenecks, and opportunities for future research and design automation.

Recommended citation: Y. Liu, R. Chen, S. Li, J. Yang, S. Li, B. da Silva. "FPGA-Based Sparse Matrix Multiplication Accelerators: From State-of-the-art to Future Opportunities." ACM TRETS, 2024. DOI: 10.1145/3687480
Download Paper

DIF-LUT Pro: An Automated Tool for Simple yet Scalable Approximation of Nonlinear Activation on FPGA

Published in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2025

DIF-LUT Pro enables simple and scalable approximation of nonlinear activation functions on FPGAs. This paper presents its automation flow and accuracy-resource tradeoffs validated on multiple benchmarks.

Recommended citation: Y. Liu, S. Li, R. Chen, Y. Li, J. Yu, K. Wang. "DIF-LUT Pro: An Automated Tool for Simple yet Scalable Approximation of Nonlinear Activation on FPGA." IEEE TCAD, 2025. DOI: 10.1109/TCAD.2025.3576333
Download Paper

TrackGNN: A Highly Parallelized and FIFO-Balanced GNN Accelerator for Track Reconstruction on FPGAs

Published in 33rd IEEE FCCM 2025, 2025

This paper proposes TrackGNN, a highly parallelized GNN accelerator designed for efficient track reconstruction in high energy physics. We introduce a FIFO-balanced architecture optimized for FPGA implementation, achieving state-of-the-art performance.

Recommended citation: S. Li, H. Zhang, R. Chen, C. Hao. "TrackGNN: A Highly Parallelized and FIFO-Balanced GNN Accelerator for Track Reconstruction on FPGAs." 33rd IEEE FCCM, 2025.
Download Paper

talks

teaching

Teaching experience 1

Undergraduate course, University 1, Department, 2014

This is a description of a teaching experience. You can use markdown like any other post.

Teaching experience 2

Workshop, University 1, Department, 2015

This is a description of a teaching experience. You can use markdown like any other post.